Conventionally, semiconductor memory devices have been provided with spare memory cells or redundant memory cells in order to improve yield. When a defect occurs in an original memory cell, the aforementioned redundant memory cell can be used as a memory cell designed to repair the aforementioned memory cell with the defect.
This type of semiconductor memory device is equipped with components such as redundant memory cells and redundant circuitry used to select and activate the aforementioned redundant memory cells.
The aforementioned redundant memory cells are arranged in terms of two directions: the horizontal (ROW) direction and the vertical (COLUMN) direction. When the address of a defective memory cell is decoded by a redundant decoder, the original memory cell and the aforementioned redundant memory cell are switched according to the address, thereby repairing the defective memory cell.
FIG. 9 is a block diagram which shows the structure of a redundant circuit in a conventional semiconductor memory device. Address data (200), in binary code, is inputted via A0-A12 to the latch circuit (not shown) of an address buffer (51).
The latch circuit (not shown) of the aforementioned address buffer (51) outputs a binary code (201) through B0-B12 to redundant decoders (52, 52', and 52").
For example, the address of a defective cell to be repaired may first be programmed into the redundant decoder (52) by blowing a fuse of fuses. The aforementioned fuse is composed of polysilicon, etc., and occupies an area of nearly 14 .mu.m (vertical) by 7 .mu.m (horizontal).
The aforementioned redundant decoder (52) comprises a discriminator circuit (not shown), which serves to determine whether or not there is a coincidence between the address of the defective memory cell to be repaired, and the address corresponding to the binary code (201) outputted from the latch circuit (not shown) of the aforementioned address buffer (51).
The discriminator circuit (not shown) of the aforementioned redundant decoder (52) outputs a driver drive signal (202) to activate a redundant line driver (53) when the address of the cell to be repaired coincides with the address corresponding to the binary code (201).
When the aforementioned redundant line driver (53) is activated, the redundant line connected to a redundant memory cell (55) is driven. As a result, the normal row or normal column is replaced with the redundant line, thereby repairing the defective memory cell.
The discriminator circuit (not shown) of the aforementioned redundant decoder (52) does not output a driver drive signal (202) when the address of the defective memory cell to be repaired does not coincide with the address corresponding to the binary code (201). As a result, the redundant line driver (53) is not activated, and the redundant line is not driven.
The redundant decoder of the redundant circuit in the aforementioned type of semiconductor memory device is designed to set the address of the defective memory cell through the action of a fuse. Since a laser is used to blow the aforementioned fuse, it is necessary to install other circuits in addition to the redundant circuit, which is problematic in terms of "space margin" in that a considerably larger area is required for forming the redundant circuit.
In addition, this difficulty has become an even greater problem in recent years because the number of fuses has increased with the higher levels of integration now used in devices.
In relation to this, one conventional solution has been to reduce the number of fuses in the redundant circuit, thereby reducing the area in which the redundant circuit is formed, without improving the repairing efficiency of the defective memory cells in the semiconductor memory device.
As an example, the numbers of fuses used in the ROW redundant circuits of 4 MB DRAM and 16 MB DRAM will be discussed.
4 MB DRAM is designed to have 16 fuses per single redundant decoder, in 32 arrays, with 2 redundant ROWs for every 2 arrays. When the number of redundant lines and redundant decoders are designed to exist in a 2:1 ratio, 32 redundant decoders are required. Thus, the number of fuses required for a single chip is 512. As a result, the minimum amount of space required for forming the fuses will be 512.times.(7.times.14) .mu.m.sup.2.
In contrast, 16 MB DRAM is designed to have 12 fuses per single redundant decoder, in 64 arrays, with 4 redundant ROWs for each array. When the number of redundant lines and redundant decoders are designed to exist in a 2:1 ratio, 128 redundant decoders are required. Thus, the number of fuses required for a single chip is 1536. As a result, with a 16 MB DRAM, the minimum amount of space required for forming the fuses will be 1536.times.(7.times.14) .mu.m.sup.2. Thus, the space required for forming the redundant circuit is increased, which is problematic in that the size of the memory chip is increased.
In relation to this, the aforementioned semiconductor memory device is designed on the principle of flexible decoding, which is a method serving to reduce the number of redundant decoders.
For example, when flexible decoding is used with the aforementioned 16 MB DRAM, it is possible to reduce the number of redundant decoders from 128 to 12. Thus, it is possible to dramatically reduce the number of fuses on a single chip: from 1536 to 144.
However, with the aforementioned semiconductor memory device, since binary code is used in the discriminator circuit (serving to determine whether or not there is a match with the address of the redundant decoder), it has not been possible up to this point to develop redundant decoders which can be programmed so as to be capable of handling all cases of neighboring defective cells. Reasons for this include the fact that the corresponding circuitry is made more complex and that the size is increased excessively.
In relation to this, the present invention provides a redundant circuit which makes it possible, using a single redundant decoder, to repair defects generated at one or two neighboring addresses. It has the objective of making it possible to easily increase the integration level and increase memory capacity through reducing the number of fuses in the redundant circuit.